Instruction set compiled simulation A technique for fast and

Instruction Set Compiled Simulation:A Technique for Fast and Flexible Instruction Set Simulation Mehrdad Reshadi Prabhat Mishra Nikil Dutt

Architectures and Compilers for Embedded Systems(ACES)Laboratory Center for Embedded Computer Systems,University of California,Irvine,CA92697,USA

(reshadi,pmishra,dutt)@7d430e3c5727a5e9856a6117

7d430e3c5727a5e9856a6117/?aces

ABSTRACT

Instruction set simulators are critical tools for the explo-ration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure,performance is the most important fea-ture of an instruction-set simulator.Interpretive simulators are?exible but slow,whereas compiled simulators deliver speed at the cost of?exibility.This paper presents a novel technique for generation of fast instruction-set simulators that combines the bene?t of both compiled and interpre-tive simulation.We achieve fast instruction accurate simu-lation through two mechanisms.First,we move the time-consuming decoding process from run-time to compile time while maintaining the?exibility of the interpretive simula-tion.Second,we use a novel instruction abstraction tech-nique to generate aggressively optimized decoded instruc-tions that further improves simulation performance.Our instruction set compiled simulation(IS-CS)technique deliv-ers upto40%performance improvement over the best known published result that has the?exibility of interpretive simu-lation.We illustrate the applicability of the IS-CS technique using the ARM7embedded processor.

Categories and Subject Descriptors

I.6.5[Simulation And Modeling]:Model Development;

I.6.7[Simulation And Modeling]:Simulation Support Systems

General Terms

Design,Performance

Keywords

Compiled Simulation,Interpretive Simulation,Instruction Set Architectures,Instruction Abstraction

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DAC2003,June2–6,2003,Anaheim,California,USA.

Copyright2003ACM1-58113-688-9/03/0006...$5.00.1.INTRODUCTION

An instruction-set simulator is a tool that runs on a host machine to mimic the behavior of running an application program on a target machine.Instruction-set simulators are indispensable tools in the development of new programmable architectures.They are used to validate an architecture de-sign,a compiler design,as well as to evaluate architectural design decisions during design space exploration. Traditional interpretive simulation is?exible but slow.In this technique,an instruction is fetched,decoded,and exe-cuted at run time as shown in Figure1.Instruction decoding is a time consuming process in a software

simulation.

Figure1:Traditional Interpretive Simulation Flow Compiled simulation performs compile time decoding of application program to improve the simulation performance as shown in Figure2.To improve the simulation speed fur-ther,static compilation based techniques move the instruc-tion scheduling into the compilation phase[4].However,all compiled simulators rely on the assumption that the com-plete program code is known before the simulation starts and is further more run-time static.Due to this assumption many application domains are excluded from the utilization of compiled simulators.For example,embedded systems that use external program memories can not use compiled simulators since the program code is not predictable prior to runtime.Similarly,compiled simulators are not applicable in embedded systems that use processors having multiple instruction sets.These processors can switch to a di?erent instruction set mode at run time.For instance,the ARM processor uses the Thumb(reduced bit-width)instruction set to reduce power and memory consumption.This dy-namic switching of instruction set modes cannot be consid-ered by a simulation compiler,since the selection depends on run-time values and is not predictable.Furthermore, applications with run-time dynamic program code,as pro-

vided by operating systems (OS),can not be addressed by compiled

simulators.

Figure 2:Traditional Compiled Simulation Flow Due to the restrictiveness of the compiled technique,in-terpretive simulators are typically used in embedded sys-tems design ?ow.This paper presents a novel technique for generation of fast instruction-set simulators that com-bines the performance of traditional compiled simulation with the ?exibility of interpretive simulation.Our instruc-tion set compiled simulation (IS-CS)technique achieves high performance due to two reasons.First,the time consuming instruction decoding process is moved to compile time while maintaining the ?exibility of interpretive simulation.In case an instruction is modi?ed at run-time,the instruction is re-decoded prior to execution.Second,we use an instruction abstraction technique to generate aggressively optimized de-coded instructions that further improve simulation perfor-mance.The IS-CS technique delivers better performance than other published simulation techniques that have the ?exibility of interpretive simulation.The simulation perfor-mance of the IS-CS technique is upto 40%better than the best known results [1]in this category.

The rest of the paper is organized as follows.Section 2presents related work addressing instruction-set simulation techniques.The instruction set compiled simulation (IS-CS)technique is presented in Section 3.Section 4presents sim-ulation results using the ARM7architecture,a commonly used embedded processor.Section 5concludes the paper.

2.RELATED WORK

An extensive body of recent work has addressed instruction-set architecture simulation.The wide spectrum of today’s instruction-set simulation techniques includes the most ?ex-ible but slowest interpretive simulation and faster compiled simulation.Recent research addresses retargetability of in-struction set simulators using a machine description lan-guage.

Simplescalar [3]is a widely used interpretive simulator that does not have any performance optimizations for func-tional simulation.

Shade [5],Embra [10]and FastSim [8]simulators use dy-namic binary translation and result caching to improve sim-ulation performance.Embra provides the highest ?exibility with maximum performance but is not retargetable:it is restricted to the simulation of the MIPS R3000/R4000ar-chitecture.

A fast and retargetable simulation technique is presented in [6].It improves traditional static compiled simulation by aggressive utilization of the host machine resources.Such utilization is achieved by de?ning a low level code gener-ation interface specialized for ISA simulation,rather than the traditional approaches that use C as a code generation interface.

Retargetable fast simulators based on an Architecture De-scription Language (ADL)have been proposed within the framework of F ACILE [9],Sim-nML [12],ISDL [14],MI-MOLA [16],ANSI C [11],LISA ([1],[2],[4]),and EXPRES-SION [15].The simulator generated from a F ACILE de-scription utilizes the Fast Forwarding technique to achieve reasonably high performance.All of these simulation ap-proaches assumes that the program code is run-time static.In summary,none of the above approaches (except [1])combines retargetability,?exibility,and high simulation per-formance at the same time.A just-in-time cache compiled simulation (JIT-CCS)technique is presented in [1].The ob-jective of the JIT-CCS technique is similar to the one pre-sented in this paper -combining the full ?exibility of inter-pretive simulators with the speed of the compiled principle.The JIT-CCS technique integrates the simulation compiler into the simulator.The compilation of an instruction takes place at simulator run-time,just-in-time before the instruc-tion is going to be executed.Subsequently,the extracted information is stored in a simulation cache for direct reuse in a repeated execution of the program address.The simula-tor recognizes if the program code of a previously executed address has changed and initiates a re-compilation.This technique makes an assumption to get performance closer to complied simulation:the number of repeatedly executed instructions should be very large such that 90%of the ex-ecution time is spent in 10%of the code.This assumption may not hold true for all real world applications.For exam-ple,the 176.gcc benchmark from SPEC CPU2000violates this rule.

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