linux系统下ncverilog的详细命令

ncverilog: 08.10-p002: (c) Copyright 1995-2008 Cadence Design Systems, Inc. Usage: ncverilog [options] files File languages: Verilog, SystemVerilog, VHDL, e, System-C, C, C++ In addition to the dash options all ncverilog plus options can be used. Options shown below in lowercase can also be entered in uppercase. For example, both -top and -TOP are valid. If you need more information about an option listed below, use the search facility in the online help system. In the \ enter the name of the option, including the dash (-profile, for example).

+access<+/-rwc> Turn on read, write and/or connectivity access +allow_unused_properties Allow simulator to enable all properties -allowredefinition Allow mutiple files to define the same object +amsconnrules+ specify connect rules to use

+amsmatlab Dynamically link vpi code for AMS/Matlab -amsmt_enable to enable AMS multithread capability -amsmt_nthreads number of threads for AMS multithreading. -amsvhdl_ext Override extensions for VHDL AMS sources +append_key Append keystrokes to existing key file -arr_access Allow tf_nodeinfo access to Verilog arrays -asext Add extensions to assembly sources +assert Enable PSL language features

+assert_count_traces Use trace-based counting for assertions +assert_sc Enable PSL language features +assert_vhdl Enable PSL language features +assert_vlog Enable PSL language features

-bb_celldefine Blackbox all verilog modules within `celldefine -bb_nonsynth Blackbox unsynthesizable modules in halsynth

-bb_unbound_comp Ignore unbounded component for synthesis checks -bb_vital Blackbox design-units containing VITAL constructs -c Parse and elaborate, do NOT simulate

-catcxx Positional option used to combine C++ sources -catcxxsize Sets the CATCXX partition size for large groups -categories List the categories and their descriptions -ccext Add extensions to C sources

-check Specify checks and categories of checks +checkargs Check command-line arguments for validity -clean Deletes previous INCA_libs directory if is exists -comb_depth Enable Logic Depth calculation +compile Parse only, do NOT elaborate

+controlassert+ Specifies a file containing assertion controls -cpost Compile C files after elaboration

+crshell Create shell files for import mode -cxxext Add extensions to C++ sources

-D Define a macro for the C and C++ compiler -date Print date and time when each engine is invoked -debug Equivalent to -access +rw, Specman debug -debugscript Specify a debug script file name

+define+ Define a macro from command line

-defineall Define macro from command line for all compilers +defparam+ Redefine the value of a Verilog parameter

-delay_mode Delay mode {Zero,PUnit,Unit,Path,Distr,None} +delay_mode_distributed Use distributed delay mode +delay_mode_path Use path delay mode

+delay_mode_punit Use precision unit delay mode +delay_mode_unit Use unit delay mode +delay_mode_zero Use zero delay mode

-design_facts_file Generate design facts during structural checks -design_info Design Information file

-distcomp Option used to turn distributed compilation on -distcompargs, Pass user specified argument to distributed comp -distcompjobs Number of parallel distributed compiles to run -distplat Specify underlying platform used for distrib comp -dpi Add appropriate build options for dpi designs -dpi_void_task Return value of export/import tasks will be VOID. +dut_prof+ Profiler report contains summary for design unit -dynamic Build a shared object for simulation

-dynvhpi Enable user to create VHDL drivers at run time -efence Debug ncsim with Electric Fence. -efenceelab Debug ncelab with Electric Fence -end Terminate the list of files

-extbind Bind file for binding SV/VHDL to SV/VHDL -F Scan file for args relative to file location -f Scan file for args relative to irun invocation -forceelab Force ncelab to execute

-format Enables shorter compiling messages from ncsc_run -g Turn on C debugging -gcc_vers 3.2.3 or 4.1 Linux only -gdb Run ncsim under gdb -gdbelab Run ncelab under gdb

-gdbpath Use the provided gdb instead of what is shipped +genassert_synth_pragma Enable generating assertions from synth pragma -gnu Choose the GNU C and C++ compiler +gui Invoke the Graphical User Interface -h Print a minimal help message -hal Call hal instead of ncsim

-halargs Pass options directly to hal

-halsynth_detailcheck Perform detailed check on unsynthesizable modules +helpalias Show the different ways to enter an option +helpall Display all supported option

+helpargs Print help for all the options in use

+helpfileext Show all the file types and their extensions +helphelp Print out all the options controlling help -helpncverilog Show the ncverilog form of the options

-helpshowmin Show the minimum characters required for dash opt +helpshowsubject Show all the subjects for -helpsubject +helpsubject Display help on the specified subject +helpverbose Show the verbose help text

+helpwidth+ Set max width for help messages (def 89) -I Directory to search for C/C++ include files

+ieee1364 Report errors according to IEEE 1364 standards +import Prepare this verilog design for import to VHDL +incdir+ Specify directories to search for `include files -inst_top Specify the top-level instance for HAL analysis

-iusld Prefix `ncroot`/tools/lib path to LD_LIBRARY_PATH -iusldno Disable the -iusld option -k Set key file name

-L Directory to search for lib files -l Set logfile name

-l archive or shared library to be linked in -level Specify levels in HAL analysis

+libext+ Specify extensions to be used for the -y search +liborder Library search rule (see documentation) +librescan Library search rule (see documentation)

+libverbose Print verbose messages about instance binding -linksysc Use libsystemc.so (dynamic) or libsystemc_ar.a -lintpragma Process lint pragma in the design -loadcfc Dynamically load a CFC application -loadfmi Dynamically load an FMI library

+loadpli1= Specify the PLI1 library_name:boot_routine(s) +loadsc+ Specify SystemC lib to be dynamically loaded -loadvhpi Dynamically load a VHPI application

+loadvpi= Specify the VPI library_name:boot_routines(s) -location Print the location of the installation

-log_amsspice Place amsspice output into the specified logfile -log_hal Place the hal output into the specified logfile -logic_depth Enable Logic Depth calculation

-loop_unroll_size Specify the loop unroll limit for halsynth

+max_error_count+ Specify the maximum number of errors processed +mixesc Handle escaped identifiers in imported model

+multisource_int_delays Make interconnect timing be multisource capable +name+ Generate snapshot with specified name -native Use the native C and C++ compiler +nc64bit Invoke 64bit version

+nca_ext+ Override extensions for archive files +ncafile+ Specify an access file to be used

+ncams Force Verilog-AMS and VHDL-AMS compilation +ncamsfastspice Enable Fast SPICE simulator (UltraSim) +ncamslic Check out an AMS license

+ncamspartinfo+ +ncamsv_ext+ +ncanalogcontrol+ +ncanno_simtime +ncappend_log -ncb_environment -ncb_file -ncb_filter -ncb_format -ncb_nodefaultenv -ncb_order -ncb_report -ncb_sortby +ncbatch +ncbinding+ +ncc_ext+ +ncccargs +nccd_lexpragma +nccds_implicit_tmpdir+ +nccds_implicit_tmponly +nccdslib+ +ncchecktasks +ncchkdigdisp +ncconffile+ +ncconfflat +ncconfhier +ncconfname+ +nccontrolrelax+ +nccovdesign+ +nccovdut+ +nccoverage+ +nccovfile+ +nccovnomodeldump +nccovoverwrite +nccovtest+ Mixed-signal partition information

Override extensions for Verilog-AMS sources Specify analog simulation control file

Enable delay annotation at simulation time Append output log to existing log

Specify environment file to be loaded by Ncbrowse File for Ncbrowse to load command line arguments Filter for report generation by Ncbrowse Set the format of messages in the report

Prevent Ncbrowse from using default environment Set the order in which items are shown

Specify the report file to be created by Ncbrowse Specify a sort order to Ncbrowse for report

Run simulation in batch mode, this is the default Force explicit submodule or unit L.C:v binding Override extensions for C sources Pass arguments to the C compiler

Process preprocessor directive before lex pragmas Specify location for design data storage

Force tools to read design data only from tmpdir Specify a cds.lib file to be used

Check that all $tasks are built-in system tasks Perform digital net's discipline compatibility Generate a configuration file with the given name Requires -CONFFILE, generate a VHDL flat config Requires -CONFFILE, gen VHDL hierarchical config Requires -CONFFILE, specify output config name Enable specific relaxed VHDL interpretation Select coverage design name Select DUT for Coverage

Enable coverage instrumentation

Specify coverage instrumentation control file

Disable coverage design database (model) dumping Enable overwrite of coverage output files Select coverage test name

+nccovworkdir+ Select coverage workdir

+nccpg+ Assigns to all generics/params of this name +nccpp_ext+ Override extensions for C++ sources +ncdebug Equivalent to -access +r

+ncdefault_ext+ Override the default extension map

+ncdesign_top+ Specifies top design unit for design-top comp +ncdisable_enht Disable enhanced timing features +ncdiscapf Disable the capital F input file mode

+ncdiscipline+ Discipline to use for undisciplined digital wires +ncdisres+ Set discipline resolution

+ncdpiheader+ Create DPI header file for export functions +ncdresolution Sets discipline resolution to '-disres detailed' +ncdumpports_format+ Specify EVCD format flag for $dumpports +ncdynlib_ext+ Override extensions for dynamic library files +nce_ext+ Override extensions for e sources

-ncelab_args, Pass arguments to elaborator (ncsc_run compat)

+ncelab_compile requires -CONFILE, compile the configuration file +ncelabargs+ Pass arguments to elaborator

+ncelabexe+ Specify elaborator with statically linked PLI +ncelabfile File for generated elab options from import +ncendlib Terminate the list of library files +ncendstage Terminate the list of e stage files

+ncerror+ Increase the severity of a warning to an error +ncescapedname Print out escaped names in logfile

+ncexit Exit simulation instead of issuing a TCL prompt +ncexpand Force expansion of all vector nets

+ncextassertmsg Prints Extended Assert message Information +ncextend_tcheck_data_limit/ Relax timing check data limit

+ncextend_tcheck_reference_limit/ Relax timing check reference limit +ncfatal+ Increase the severity of a warn/error to fatal +ncgateloopwarn Enable potential zero-delay gate loop warning +ncgenafile+ Generate an access file for PLI and TCL +ncgeneric+ Associate value with top-level generic

+ncgnoforce Assigns the value if default value not found +ncgpg+ Assigns to all generics/params of this name +ncgverbose Logs the gpg activity to the ncelab logfile +nchdlvar+ Specify an hdl.var file to be used +nciereport Generate interface element report

+ncignore_defexpr Ignore default expressions on variable,signal,... +ncinitbiopz Initialize boundary inout port to 'Z' +ncinitialize+ Initialize variables in the design

+ncinitzero Enable zero initialization of time and integer +ncinput+ Read TCL commands from file

+ncinsert+ Specify string to be inserted after matching comp

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