linux系统下ncverilog的详细命令(3)

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+overwrite Overwrite existing config file of same name -ovm Turn on support for the OVM library -ovmhome

Location to look for the OVM install

+partialdesign Allow elaboration of partially-defined design +pathpulse Set pulse limits according to PATHPULSE$ -pathtran Kill pathdelays touching multiple tran gates +plimapfile= Specify VPI and/or PLI mapping file(s)

+plinooptwarn Suppress PLI messages caused by limited access +plinowarn Do not print PLI warning and error messages -precompiled_headers Use precompiled headers. Only with gcc 4.1 -printspecs Have ncsc_run print out the spec file

+profile_sc+ File containing PSL/Covergroup verification code +profile_vhdl+ File containing PSL/Covergroup verification code +propdir+

Specify directory to consider when searching +propext+ Specify extensions to consider when searching +propfile+ File containing PSL/Covergroup verification code -propfile Unsupported use -propfile_vlog|vhdl|sc

+propssc_ext+ Specify extensions to consider when searching +propvhdl_ext+ Specify extensions to consider when searching +pulse_e/ Set percentage of delay for pulse error limit +pulse_e_style_ondetect Use on-detect filtering of error pulses +pulse_e_style_onevent Use on-event filtering of error pulses +pulse_int_e/ Set percent delay for pulse error limit +pulse_int_r/ Set percent delay for pulse reject limit

+pulse_r/ Set percentage of delay for pulse error limit -purecov Instrument ncsim code with purecov -purecovelab Instrument ncelab with purecov -purify Instrument ncsim code with purify -purifyelab Instrument ncelab with purify

-Q Quiet mode, with banner and command line

-q Suppress informational messages(i.e., Quiet mode) -quantify Instrument ncsim code with quantify -quantifyelab Instrument ncelab with quantify

-R Simulate using last snapshot generated -r Force simulation using snapshot

-races Run zero-delay race condition checks

-read_lib Enable DFT, scanchain check using *.lib synthesis -read_tlf Enable DFT, scanchain check using *.tlf synthesis +rmkeyword+ Specify list of keywords to be removed -rulefile file for loading definitions of categories checks -rulelib A shared library containing user-defined checks -rules_checked Print details of the checks

-rules_list Print all the rules present in HAL

-s Load snapshot and go to the interactive prompt

-sa_force_list Provide the input file to force the modules -sc_main Run with an sc_main entry point +scAllowSCFromPLI Allow SystemC from PLI

-scautoshell SYSTEMC|HDL|VERILOG|VHDL Automatically generate shell modules +scConvertWarn Turn on X/Z -> 0 data conversion warnings

+scDisableDynamicHierarchy Disable Dynamic Hierarchy in designs with SystemC +scgafap+ Either +on +off or +auto

+scNoDestructorsInElab Do not run desctructors during elaboration

+sctop+ Specify SystemC module name to be the top level -scv Turn on linking of the CVE and SCV libraries +sdf_file+ Specify the SDF annotation file +sdf_nopulse Ignore SDF pulse information

+sdf_specpp Use PATHPULSE parameters in specify block -seed Set the seed for value

+show_cancelled_e Filter canceled events (negative pulses) to e +show_forces Turn on support for force -show

-showtoptype Show the type of the top level design unit

+simvisargs+ Quoted string of SimVision command-line arguments -snheader Have specman create a header file

+snheaderargs+ Pass arguments to snheader generation phase -snrebuild Force the recompilation of the e input files -spec Specify an alternative spec file

-spice_ext Override extensions for SPICE sources

-stats Print counts of the error/warning messages issued +sv Force SystemVerilog compilation +sv_lib= Dynamically load a DPI library

+sv_root+ Specify root path for \

+svperf+ Enable SystemVerilog UniquePriority performance -svpp Allow svpp to preprocess verilog files -svppargs Pass arguments to svpp

-svpptestcase Tar and zip the svpp simulation

+svrnc=

+systemc_args+ List of arguments to sc_main

+systemverilog_ext+ Override extensions for SystemVerilog sources -testcoverage Enable Logic Depth calculation

-timeunit_case Prints time units from std.textio in upper case -topic Lists all ncsc_run option in a group or more info +transport_int_delays Make interconnect timing be multisource capable -u Convert identifiers to uppercase

-urm Add search directories needed by the URM library -urmhome Override the default location of the URM library -v Specify a library file to be used

+v1995 Turn off new Verilog-2001 keywords

-verbose Verbose messages when compiling C or running svpp +verilog1995ext+ Override extensions for Verilog95 sources -vhcfg_ext Override extensions for VHDL config files -vhdlext Add extensions to VHDL sources

-vhdltop Specify the top-level VHDL unit to be bound to : -vic Turn off linking of the VIC libraries +vlog_ext+ Override extensions for Verilog sources -vlogext Add extensions to Verilog sources

-w Disable printing of all warning messages -warnmax Maximum warnings reported by halsynth

-Wcc, Pass user specified arguments to the C compiler -Wcxx, Pass user specified arguments to C++ compiler -Wld, Pass user specified arguments to C++ linker +work+ Library for command line Source

-Wv, Pass user specified arguments to compiler -y Specify a library directory to be used

Example commands to invoke ncverilog ncverilog sio85.v

ncverilog xor.v bot.vhd xor_verify.e ncverilog -f run.f

ncverilog a.v b.v c.vhd -c

ncverilog -R -input commands.tcl ncverilog -helpsubject specman

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